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ST24LC21B, ST24LW21 ST24FC21, ST24FC21B, ST24FW21
1 Kbit (x8) Dual Mode Serial EEPROM for VESA PLUG & PLAY
1 MILLION ERASE/WRITE CYCLES 40 YEARS DATA RETENTION 3.6V to 5.5V or 2.5V to 5.5V SINGLE SUPPLY VOLTAGE HARDWARE WRITE CONTROL (ST24LW21 and ST24FW21) TTL SCHMITT-TRIGGER on VCLK INPUT 100k / 400k Hz COMPATIBILITY with the I2C BUS BIT TRANSFER RANGE TWO WIRE SERIAL INTERFACE I2C BUS COMPATIBLE I2C PAGE WRITE (up to 8 Bytes) I2C BYTE, RANDOM and SEQUENTIAL READ MODES SELF TIMED PROGRAMMING CYCLE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD/LATCH UP PERFORMANCES ERROR RECOVERY MECHANISM (ST24FC21 and ST24FW21) VESA 2 COMPATIBLE DESCRIPTION The ST24LC21B, ST24LW21, ST24FC21, ST24FC21B and ST24FW21 are 1K bit electrically erasable programmable memory (EEPROM), organized in 128x8 bits. In the text, products are referred as ST24xy21, where "x" is either "L" for VESA 1 or "F" for VESA 2 compatible memories and where "y" indicates the Write Control pin connection: "C" means WC on pin 7 and "W" means WC on pin 3.
8 1
PSDIP8 (B) 0.25mm Frame
8 1
SO8 (M) 150mil Width
Figure 1. Logic Diagram
VCC
SCL VCLK WC ST24xy21
SDA
Table 1. Signal Names
SDA SCL VCC VSS VCLK WC Serial Data Address Input/Output
2 Serial Clock (I C mode)
VSS
AI01741
Supply Voltage Ground Clock Transmit only mode Write Control
Note: WC signal is only available for ST24LW21 and ST24FW21 products.
June 2002
1/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 2A. DIP Pin Connections Figure 2B. SO Pin Connections
ST24LC21B NC NC NC VSS 1 2 3 4 8 7 6 5
AI01742
ST24LC21B
VCC VCLK SCL SDA
NC NC NC VSS
1 2 3 4
8 7 6 5
AI01743
VCC VCLK SCL SDA
Warning: NC = Not Connected.
Warning: NC = Not Connected.
Figure 2C. DIP Pin Connections
Figure 2D. SO Pin Connections
ST24FC21 ST24FC21B NC NC DU VSS 1 2 3 4 8 7 6 5
AI01744
ST24FC21 ST24FC21B VCC VCLK SCL SDA NC NC DU VSS 1 2 3 4 8 7 6 5
AI01745
VCC VCLK SCL SDA
Warning: NC = Not Connected. DU = Don't Use, must be left open or connected to VCC or VSS.
Warning: NC = Not Connected. DU = Don't Use, must be left open or connected to VCC or VSS.
Figure 2E. DIP Pin Connections
Figure 2F. SO Pin Connections
ST24FW21 ST24LW21 NC NC WC VSS 1 2 3 4 8 7 6 5
AI01746
ST24FW21 ST24LW21 VCC VCLK SCL SDA NC NC WC VSS 1 2 3 4 8 7 6 5
AI01747
VCC VCLK SCL SDA
Warning: NC = Not Connected.
Warning: NC = Not Connected.
2/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG TLEAD VIO VCC VESD Parameter Ambient Operating Temperature Storage Temperature Lead Temperature, Soldering Input or Output Voltages Supply Voltage Electrostatic Discharge Voltage (Human Body model) Electrostatic Discharge Voltage (Machine model)
(3) (2)
Value -40 to 85 -65 to 150
Unit C C C V V V V
(SO8 package) (PSDIP8 package)
40 sec 10 sec
215 260 -0.3 to 6.5 -0.3 to 6.5 4000 500
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100pF, 1500 ). 3. EIAJ IC-121 (Condition C) (200pF, 0 ).
Table 3A. Device Select Code (ST24LC21B, ST24LW21, ST24FC21 and ST24FW21)
Device Code Bit Device Select b7 1 b6 0 b5 1 b4 0 b3 X Chip Enable b2 X b1 X RW b0 RW
Note: The MSB b7 is sent first. X = 0 or 1.
Table 3B. Device Select Code (ST24FC21B)
Device Code Bit Device Select b7 1 b6 0 b5 1 b4 0 b3 0 Chip Enable b2 0 b1 0 RW b0 RW
Note: The MSB b7 is sent first. X = 0 or 1.
DESCRIPTION (cont'd) The ST24xy21 can operate in two modes: Transmit-Only mode and I2C bidirectional mode. When powered, the device is in Transmit-Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK. The device will switch to the I2C bidirectional mode upon the falling edge of the signal applied on SCL pin. When in I2C mode, the ST24LC21B (or the ST24LW21) cannot switch back to the Transmit Only mode (except when the power supply is removed). For the ST24FC21, ST24FC21B (or the ST24FW21), after the falling edge of SCL, the memory enter in a transition state which allowed to
switch back to the Transmit-Only mode if no valid I2C activity is observed. Both Plastic Dual-in-Line and Plastic Small Outline packages are available. Transmit Only Mode After a Power-up, the ST24xy21 is in the Transmit Only mode. A proper initialization sequence (see Figure 3) must supply nine clock pulses on the VCLK pin (in order to internally synchronize the device). During this initialization sequence, the SDA pin is in high impedance. On the rising edge of the tenth pulse applied on VCLK pin, the device will output the first bit of byte located at address 00h (most significant bit first).
3/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 3. Transmit Only Mode Waveforms
VCC
SCL
SDA tVPU VCLK 1 2 8 9 10
Bit 7
Bit 6
11
VCC
SCL
SDA
Bit 6
Bit 5
Bit 4
Bit 0
Bit 7
Bit 6
VCLK
12
13
17
18
19
20
AI01501
Table 4. I2C Operating Modes
Mode RW bit ST24LC21B ST24FC21 ST24FC21B VCLK X X X X VIH VIH ST24LW21 ST24FW21 WC X X X X VIH VIH 1 to 128 1 8 Bytes Initial Sequence
Current Address Read Random Address Read Sequential Read Byte Write Page Write
Note: X = VIH or VIL
'1' '0' '1' '1' '0' '0'
1 1
START, Device Select, RW = '1' START, Device Select, RW = '0', Address, reSTART, Device Select, RW = '1' Similar to Current or Random Mode START, Device Select, RW = '0' START, Device Select, RW = '0'
4/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 4. Transition from Transmit Only (DDC1) to Bi-directional (DDC2B) Mode Waveforms
Transmit Only Mode
- Temporary Bi-Directional Mode (ST24FC21 and ST24FW21) - Locked Bi-Directional Mode (ST24LC21B and ST24LW21) 2 8 9
- Locked Bi-Directional Mode (ST24FC21 and ST24FW21)
SCL
1
SDA
MSB
ACK
VCLK
START CONDITION
AI01892
A byte is clocked out (on SDA pin) with nine clock pulses on VCLK: 8 clock pulses for the data byte and one extra clock pulse for a Don't Care bit. As long as the SCL pin is held high, each byte of the memory array is transmitted serially on the SDA pin with an automatic address increment. When the last byte is transmitted, the address counter will roll-over to location 00h. I2C Bidirectional Mode The ST24xy21 can be switched from Transmit Only mode to I2C Bidirectional mode by applying a valid high to low transition on the SCL pin (see Figure 4). - When the ST24LC21B (or the ST24FC21 or the ST24FC21B) is in the I2C Bidirectional mode, the VCLK input (pin 7) enables (or inhibits) the execution of any write instruction: if VCLK = 1, write instructions are executed; if VCLK = 0, write instructions are not executed. - When the ST24LW21 (or the ST24FW21) is in the I2C Bidirectional mode, the Write Control (WC on pin 3) input enables (or inhibits) the execution of any write instruction: if WC = 1, write instructions are executed;if WC = 0, write instructions are not executed. The ST24xy21 is compatible with the I2C standard, two wire serial interface which uses a bidirectional data bus and serial clock. The ST24xy21 carries a built-in 4 bit, unique device identification code (1010) named Device Select code corresponding to the I2C bus definition. The ST24LC21B carries a unique device identification code (1010.0000 RW)
named Device Select code corresponding to the I2C bus definition. The ST24xy21 behaves as a slave device in the I2C protocol with all memory operations synchronized by the serial clock SCL. Read and write operations are initiated by a START condition generated by the bus master. The START condition is followed by a stream of 7 bits, plus one read/write bit and terminated by an acknowledge bit. When data is written into the memory, the ST24xy21 responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it must acknowledge the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condition (see READ and WRITE descriptions in the following pages). Power On Reset: VCC lock out write protect In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is implemented. Until the VCC voltage has reached the POR threshold value, the internal reset is active, all operations are disabled and the device will not respond to any command. In the same way, when VCC drops down from the operating voltage to below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable VCC must be applied before applying any logic signal. Error Recovery Modes available in the ST24FC21, ST24FC21B and the ST24FW21
5/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 5. Error Recovery Mechanism Flowchart for the ST24FC21, ST24FC21B and ST24FW21 products
Memory Power On Internal Address Pointer = 0
VCLK
YES Send Data bit (MSB first) pointed by the Address Pointer and auto-increment pointed bit/byte Transmit-Only Mode (DDC1)
NO
NO
SCL
YES SDA Hi-Z VCLK Internal Counter = 0 Start Internal 2 sec Timer
SCL
YES Reset VCLK Internal Counter and Reset Internal Timer
NO
Valid I2C access (START + Device Select) ? Transition State (VESA 2) NO VCLK
YES
I2C communication idle waiting for a Device Select byte
YES Increment VCLK Counter
Reset Counter and Timer
I2C Mode (DDC2B)
Send Acknowledge
NO
Counter = 128 or Timer > 2 sec YES Switch Back to Transmit-Only Mode
Respond to the Incoming I2C Command
AI01748
6/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 6. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
VCC 20
Maximum RP value (k)
16 RL 12 8 4 0 10 100 CBUS (pF)
AI01665
RL
SDA MASTER fc = 100kHz fc = 400kHz SCL CBUS
CBUS 1000
When the ST24FC21 (or the ST24FC21B or the ST24FW21) first switches to the I2C mode (VESA DDC2B mode), it enters a transition state which is functionally identical to I2C operation. But, if the ST24FC21 (or the ST24FC21B or the ST24FW21) does not receive a valid I2C sequence, that is a START condition followed by a valid Device Select co de (10 10XXX RW f o r ST 2 4F C 21 an d ST24FW21; 1010000 RW for ST24FC21B), within either 128 VCLK periods or a period of time of t RECOVERY (approximat ely 2 seconds), the ST24FC21 (or the ST24FC21B or the ST24FW21) will revert to the Transmit-Only mode (VESA DDC1 mode). If the ST24FC21 (or the ST24FC21B or the ST24FW21) decodes a valid I2C Device Select code, it will lock into I2C mode. Under this condition, signals applied on the VCLK input will not disturb READ access from the ST24FC21 (or the ST24FC21B or the ST24FW21). For WRITE access, refer to the Signal Description paragraph. When in the transition state, the count of VCLK pulses and the internal 2 seconds timer are reset by any activity on the SCL line. This means that, after each high to low transition on SCL, the memory will re-initialise its transition state and will switch back to Transmit-Only mode only after 128 more VCLK pulses or after a new tRECOVERY delay. SIGNAL DESCRIPTIONS
I2C Serial Clock (SCL). The SCL input pin is used to synchronize all data in and out of the memory. A resistor can be connected from the SCL line to VCC to act as a pull up (see Figure 6). Serial Data (SDA). The SDA pin is bi-directional and is used to transfer data in or out of the memory. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A resistor must be connected from the SDA bus line to VCC to act as pull up (see Figure 6). Transmit Only Clock (VCLK). The VCLK input pin is used to synchronize data out when the ST24xy21 is in Transmit Only mode. For the ST24LC21B and the ST24FC21 or ST24FC21B Only, the VCLK offers also a Write Enable (active high) function when the ST24LC21B and the ST24FC21 or ST24FC21B are in I2C bidirectional mode. Write Control (WC). An hardware Write Control feature (WC) is offered only on ST24LW21 and ST24FW21 on pin 3. This feature is usefull to protect the contents of the memory from any erroneous erase/write cycle. The Write Control signal is used to enable (WC = VIL) or disable (WC = VIH) the internal write protection. When unconnected, the WC input is internally tied to VSS by a 100k ohm pull-down resistor and the memory is write protected. DEVICE OPERATION
7/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Table 5. Input Parameters (1) (TA = 25 C, f = 100 kHz )
Symbol CIN CIN tLP Parameter Input Capacitance (SDA) Input Capacitance (other pins) Low-pass filter input time constant (SDA and SCL) 200 Test Condition Min Max 8 6 500 Unit pF pF ns
Note: 1. Sampled only, not 100% tested.
Table 6A. DC Characteristics (ST24LC21B, ST24LW21, ST24FC21 and ST24FW21) (TA = -40 to 85 C; VCC = 3.6V to 5.5V)
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current Test Condition 0V VIN VCC 0V VOUT VCC SDA in Hi-Z VCC = 5V, fC = 400kHz (Rise/Fall time < 10ns) VCC = 3.6V, fC = 400kHz VIN = VSS or VCC, VCC = 5V, fC = 0 VIN = VSS or VCC, VCC = 5V, fC = 400kHz Supply Current (Standby) VIN = VSS or VCC, VCC = 3.6V, fC = 0 VIN = VSS or VCC, VCC = 3.6V, fC = 400kHz VIL VIH Input Low Voltage (SCL, SDA, WC) Input High Voltage (SCL, SDA, WC) High Level Threshold Voltage (Schmitt Trigger on VLCK) VCC = 5.5V VCC = 4.5V VCC = 3.6V VN Low Level Threshold Voltage (Schmitt Trigger on VLCK) VCC = 5.5V VCC = 4.5V VCC = 3.6V VH Hysteresis Voltage (Schmitt Trigger on VLCK) VCC = 5.5V VCC = 4.5V VCC = 3.6V VOL Output Low Voltage IOL = 3mA, VCC = 3.6V IOL = 6mA, VCC = 5V -0.3 0.7 VCC 1.4 1.2 1 0.6 0.5 0.4 0.4 0.4 0.35 Min Max 2 2 2 1 100 300 30 100 0.3 VCC VCC + 1 2.1 1.9 1.7 1.4 1.2 1 1.5 1.4 1.3 0.4 0.6 Unit A A mA mA A A A A V V V V V V V V V V V V V
ICC
ICC1
Supply Current (Standby)
ICC2
VP
8/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Table 6B. DC Characteristics (ST24FC21B) (TA = -40 to 85 C; VCC = 2.5 to 5.5V)
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current Test Condition 0V VIN VCC 0V VOUT VCC SDA in Hi-Z VCC = 5V, fC = 400kHz (Rise/Fall time < 10ns) VCC = 2.5V, fC = 400kHz VIN = VSS or VCC, VCC = 5V, fC = 0 VIN = VSS or VCC, VCC = 5V, fC = 400kHz Supply Current (Standby) VIN = VSS or VCC, VCC = 2.5V, fC = 0 VIN = VSS or VCC, VCC = 2.5V, fC = 400kHz VIL VIH VP Input Low Voltage (SCL, SDA, WC) Input High Voltage (SCL, SDA, WC) High Level Threshold Voltage (Schmitt Trigger on VLCK) Low Level Threshold Voltage (Schmitt Trigger on VLCK) Output Low Voltage VCC = 5.0V VCC = 2.5V VCC = 5.0V VCC = 2.5V IOL = 2.1mA, VCC = 2.5V IOL = 6mA, VCC = 5V
Note 1: Preliminary results.
Min
(1)
Max
(1)
Unit A A mA mA A A A A V V V V V V V V
2 2 2 1 100 300 30 100 -0.3 0.7 VCC 1.2 0.8 0.6 0.5 0.3 VCC VCC + 1 1.9 1.4 1.7 1.1 0.4 0.6
ICC
ICC1
Supply Current (Standby)
ICC2
VN
VOL
9/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Table 7. AC Characteristics, I2C Bidirectional Mode for Clock Frequency = 400kHz (TA = -40 to 85 C; VCC = 3.6 to 5.5V or VCC = 2.5 to 5.5V)
Symbol tCH1CH2 tCL1CL2 tDH1DH2 tDL1DL2
(1) (1) (1) (1)
Alt tR tF tR tF tSU:STA tHIGH tHD:STA tHD:DAT tLOW tSU:DAT tSU:STO tBUF tAA tDH fSCL tWR Clock Rise Time Clock Fall Time SDA Rise Time SDA Fall Time
Parameter
Min
Max 300 300
Unit ns ns ns ns ns ns ns s s ns ns s
20 20 600 600 600 0 1.3 100 600 1.3 200 200
300 300
tCHDX (2) tCHCL tDLCL tCLDX tCLCH tDXCX tCHDH tDHDL tCLQV tCLQX fC tW
Clock High to Input Transition Clock Pulse Width High Input Low to Clock Low (START) Clock Low to Input Transition Clock Pulse Width Low Input Transition to Clock Transition Clock High to Input High (STOP) Input High to Input Low (Bus Free) Clock Low to Data Out Valid Clock Low to Data Out Transition Clock Frequency Write Time
900
ns ns
400 10
kHz ms
Notes: 1. Sampled only, not 100% tested. 2. For a reSTART condition, or following a write cycle.
I2C Bus Background The ST24xy21 supports the I2C protocol. This protocol defines any device that sends data onto the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master will always initiate a data transfer and will provide the serial clock for synchronisation. The ST24xy21 are always slave devices in all communications. Start Condition. START is identified by a high to low transition of the SDA line while the clock SCL is stable in the high state. A START condition must precede any command for data transfer. Except during a programming cycle, the ST24xy21 continuously monitor the SDA and SCL signals for a START condition and will not respond unless one is given. The ST24LC21B, ST24LW21, ST24FC21 and ST24FW21 are not executing a START condition if this START condition happens at any time inside a byte. The ST24FC21B executes a START condition when this START condition happens at any time inside a byte.
Stop Condition. STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communication between the ST24xy21 and the bus master. A STOP condition at the end of a Read command (after the No ACK) forces the standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle. The ST24LC21B, ST24LW21, ST24FC21 and ST24FW21 are not executing a STOP condition if this STOP condition happens at any time inside a byte. The ST24FC21B executes a STOP condition when this STOP condition happens at any time inside a byte. Acknowledge Bit (ACK). An acknowledge signal is used to indicate a successfull data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse period the receiver pulls the SDA bus low to acknowledge the receipt of the 8 bits of data. Data Input. During data input, the ST24xy21 sample the SDA bus signal on the rising edge of the clock SCL. Note that for correct device operation
10/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Table 8. AC Characteristics, I2C Bidirectional Mode for Clock Frequency = 100kHz (TA = -40 to 85 C; VCC = 3.6V to 5.5V)
Symbol tCH1CH2 tCL1CL2 tDH1DH2 tDL1DL1 tCHDX (1) tCHCL tDLCL tCLDX tCLCH tDXCX tCHDH tDHDL tCLQV
(2)
Alt tR tF tR tF tSU:STA tHIGH tHD:STA tHD:DAT tLOW tSU:DAT tSU:STO tBUF tAA tDH fSCL tWR Clock Rise Time Clock Fall Time Input Rise Time Input Fall Time
Parameter
Min
Max 1 300 1 300
Unit s ns s ns s s s s s ns s s
Clock High to Input Transition Clock Pulse Width High Input Low to Clock Low (START) Clock Low to Input Transition Clock Pulse Width Low Input Transition to Clock Transition Clock High to Input High (STOP) Input High to Input Low (Bus Free) Clock Low to Next Data Out Valid Data Out Hold Time Clock Frequency Write Time
4.7 4 4 0 4.7 250 4.7 4.7 0.2 200 100 10 3.5
s ns kHz ms
tCLQX fC tW
Notes: 1. For a reSTART condition, or following a write cycle. 2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP conditions.
Table 9. AC Characteristics, Transmit-only Mode (TA = -40 to 85 C; VCC = 3.6V to 5.5V)
Symbol tVCHQX tVCHVCL tVCLVCH tCLQZ tVPU
(1,2)
Alt tVAA tVHIGH tVLOW tVHZ
Parameter Output Valid from VCLK VCLK High Time VCLK Low Time Mode Tansition Time Transmit-only Power-up Time
Min
Max 500
Unit ns ns s
600 1.3 500 0 1 1 1.5 3.5
ns ns s s sec
tVH1VH2 (2) tVL1VL2
(2) (2)
tR tF
VCLK Rise Time VCLK Fall Time Recovery Time
tRECOVERY
Notes: 1. Refer to Figure 3. 2. Sampled only, not 100% tested.
11/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 7. AC Waveforms
tCHCL SCL tDLCL SDA IN tCHDX START CONDITION tCLDX SDA INPUT SDA CHANGE
tCLCH
tDXCX
tCHDH
tDHDL STOP & BUS FREE
SCL tCLQV SDA OUT DATA VALID tCLQX
DATA OUTPUT
tDHDL SCL tW SDA IN tCHDH STOP CONDITION WRITE CYCLE tCHDX START CONDITION
tVCHVCL VCLK tVCHQX SDA
tVCLVCH
tCLQZ SCL
AI01503
12/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Table 10. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages SDA, SCL Input Pulse Voltages VCLK Input and Output Timing Ref. Voltages 50ns 0.2VCC to 0.8VCC 0.4V to 2.4V 0.3VCC to 0.7VCC
0.2VCC 0.8VCC 0.7VCC 0.3VCC
AI00825
Figure 8. AC Testing Input Output Waveforms
Figure 9. I2C Bus Protocol
SCL
SDA START CONDITION SDA INPUT SDA CHANGE STOP CONDITION
SCL
1
2
3
7
8
9
SDA
MSB
ACK
START CONDITION
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP CONDITION
AI00792
13/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 10. Write Cycle Polling using ACK
WRITE Cycle in Progress
START Condition DEVICE SELECT with RW = 0
NO First byte of instruction with RW = 0 already decoded by ST24xxx
ACK Returned YES
NO
Next Operation is Addressing the Memory
YES
ReSTART
Send Byte Address
STOP
Proceed WRITE Operation
Proceed Random Address READ Operation
AI01099B
the SDA signal must be stable during the clock low to high transition and the data must change ONLY when the SCL line is low. Memory Addressing. To start communication between the bus master and the slave ST24xy21, the master must initiate a START condition. Following this, the master sends onto the SDA bus line 8 bits (MSB first) corresponding to the Device Select code (7 bits) and a READ or WRITE bit. The 4 most significant bits of the Device Select code are the device type identifier, corresponding to the I2C bus definition. For these memories the 4 bits are fixed as 1010b. The 8th bit sent is the read or write bit (RW), this bit is set to '1' for read and '0' for write operations. If a match is found, the corresponding
memory will acknowledge the identification on the SDA bus during the 9th bit time. Write Operations Following a START condition the master sends a Device Select code with the RW bit set to '0'. The memory acknowledges this and waits for a byte address. After receipt of the byte address the device again responds with an acknowledge. In I2C bidirectional mode, any write command with VCLK=0 (for the ST24LC21B and ST24FC21, ST24FC21B) or with WC=0 (for the ST24LW21 and ST24FW21) will not modify data and will be acknowledged on data bytes, as shown in Figure 12. Byte Write. In the Byte Write mode the master sends one data byte, which is acknowledged by the
14/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 11. Write Modes Sequence
VCLK/WC ACK BYTE WRITE START DEV SEL R/W ACK DATA IN STOP ACK DATA IN 1 ACK DATA IN 2 BYTE ADDR R/W STOP
AI01893
ACK
BYTE ADDR
VCLK/WC ACK PAGE WRITE START ACK DATA IN N DEV SEL
ACK
memory. The master then terminates the transfer by generating a STOP condition. Page Write. The Page Write mode allows up to 8 bytes to be written in a single write cycle, provided that they are all located in the same 'row' in the memory: that is the most significant memory address bits are the same. The master sends from one up to 8 bytes of data, which are each acknowledged by the memory. After each byte is transfered, the internal byte address counter (3 least significant bits only) is incremented. The transfer is terminated by the master generating a STOP condition. Care must be taken to avoid address counter 'roll-over' which could result in data being overwritten. Note that, for any write mode, the generation by the master of the
STOP condition starts the internal memory program cycle. All inputs are disabled until the completion of this cycle and the memory will not respond to any request. Minimizing System Delays by Polling On ACK. During the internal write cycle, the memory disconnects itself from the bus in order to copy the data from the internal latches to the memory cells. The maximum value of the write time (tW) is given in the AC Characteristics table, since the typical time is shorter, the time seen by the system may be reduced by an ACK polling sequence issued by the master. The sequence is as follows: - Initial condition: a Write is in progress (see Figure 10).
15/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 12. Inhibited Write when VCLK/WC = 0
VCLK/WC CONTROL BYTE
ACK WORD ADDR DATA
ACK
BYTE WRITE
START
ACK
CONTROL BYTE
ACK WORD ADD n DATA n
ACK DATA n + 1
STOP
ACK DATA n + 7
ACK
PAGE WRITE
START
ACK
STOP
AI01894
- Step 1: the Master issues a START condition followed by a Device Select byte (1st byte of the new instruction). - Step 2: if the memory is busy with the internal write cycle, no ACK will be returned and the master goes back to Step 1. If the memory has terminated the internal write cycle, it will respond with an ACK, indicating that the memory is ready to receive the second part of the instruction (the first byte of this instruction was already sent during Step 1). Read Operations On delivery, the memory content is set at all "1's" (or FFh). Current Address Read. The memory has an internal byte address counter. Each time a byte is read, this counter is incremented. For the Current Address Read mode, following a START condition, the master sends the Device Select code with the RW bit set to '1'. The memory acknowledges this and outputs the data byte addressed by the internal byte address counter. This counter is then incremented. The master must NOT acknowledge the data byte output and terminates the transfer with a STOP condition.
Random Address Read. A dummy write is performed to load the address into the address counter, see Figure 14. This is followed by a ReSTART condition send by the master and the Device Select code is repeated with the RW bit set to '1'. The memory acknowledges this and outputs the addressed data byte. The master must NOT acknowledge the data byte output and terminates the transfer with a STOP condition. Sequential Read. This mode can be initiated with either a Current Address Read or a Random Address Read. However, in this case the master DOES acknowledge the data byte output and the memory continues to output the next byte in sequence. To terminate the stream of bytes, the master must NOT acknowledge the last data byte output, and MUST generate a STOP condition. The output data is from consecutive byte addresses, with the internal byte address counter automatically incremented after each byte output. After a count of the last memory address, the address counter will 'roll-over' and the memory will continue to output data. Acknowledge in Read Mode. In all read modes the ST24xy21 wait for an acknowledge during the 9th bit time. If the master does not pull the SDA line
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ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 13. Recommended Schematic for VESA 2.0 Specification
+5V
9
+5V Monitor
47k
VCC
SCL SDA VSync
15 12 14
SCL 100nF SDA VCLK VSS
HOST
VGA Cable
MONITOR
AI01749
low during this time, the ST24xy21 terminate the data transfer and switches to a standby state. NOTE CONCERNING THE POWER SUPPLY VOLTAGE IN THE VESA 2.0 SPECIFICATION According to the VESA 2.0 specification, the ST24xy21 can be supplied by either the MONITOR or by the HOST (using +5V on the VGA cable pin 9) power supply. The easyest way to implement this is to use 2 diodes as described in the following
schematic. The ST24xy21 supply voltage will be decreased by 0.6V, which is the diode forward voltage drop, and will be below 4.5V. Nevertheless, the ST24xy21 remains operational and no input will be damaged if the applied voltage on any input complies with the Absolute Maximum Ratings values. Under this condition, the threshold voltage of the Schmitt-Trigger (pin 7) will be decreased (as in Table 6).
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ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 14. Read Modes Sequence
ACK CURRENT ADDRESS READ DEV SEL
NO ACK DATA OUT
START
R/W
ACK RANDOM ADDRESS READ DEV SEL *
ACK DEV SEL *
STOP
ACK
NO ACK DATA OUT
BYTE ADDR
START
START
R/W
R/W
ACK SEQUENTIAL CURRENT READ DEV SEL
ACK
ACK
NO ACK
DATA OUT 1 R/W
DATA OUT N
START
ACK SEQUENTIAL RANDOM READ DEV SEL *
ACK DEV SEL *
ACK
ACK
BYTE ADDR
DATA OUT 1
START
R/W
START
R/W
ACK
NO ACK
DATA OUT N
STOP
AI00794C
Note: * The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.
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STOP
STOP
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
ORDERING INFORMATION SCHEME
Example:
ST24LC21B
M
1
TR
Family Range ST24LC21B ST24LW21 ST24FC21 VESA 1 WC on pin 7 VESA 1 WC on pin 3 B M
Package PSDIP8 0.25mm Frame SO8 150mil Width
Temperature Range 1 6 0 to 70 C -40 to 85 C
Option TR Tape & Reel Packing
VESA 2 WC on pin 7 Device Select=1010.xxx
ST24FC21B VESA 2, 2.5V WC on pin 7 Device Select=1010.000 ST24FW21 VESA 2 WC on pin 3
Devices are shipped from the factory with the memory content set at all "1's" (FFh). For a list of available options (Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
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ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
Symb Typ A A1 A2 B B1 C D E E1 e1 eA eB L N
PSDIP8
mm Min 3.90 0.49 3.30 0.36 1.15 0.20 9.20 7.62 - 6.00 2.54 - 7.80 Max 5.90 - 5.30 0.56 1.65 0.36 9.90 - 6.70 - - 10.00 3.00 8 3.80 0.100 0.300 Typ
inches Min 0.154 0.019 0.130 0.014 0.045 0.008 0.362 - 0.236 - 0.307 Max 0.232 - 0.209 0.022 0.065 0.014 0.390 - 0.264 - - 0.394 0.118 8 0.150
A2 A1 B B1 D
N
A L eA eB C
e1
E1
1
E
PSDIP-a
Drawing is not to scale.
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ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
SO8 - 8 lead Plastic Small Outline, 150 mils body width
Symb Typ A A1 B C D E e H h L N CP
SO8
mm Min 1.35 0.10 0.33 0.19 4.80 3.80 1.27 - 5.80 0.25 0.40 0 8 0.10 Max 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ
inches Min 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8
h x 45 A C B e D CP
N
E
1
H A1 L
SO-a
Drawing is not to scale.
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ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Information furnished is believed to be accurate and reliable. However, STMicroelectroni cs assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners Purchase of I2C Components by STMicroelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in an I 2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - United States http://www.st.com
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